93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN DESCRIPTIONS
Name
CS
CLK
DI
DO
V SS
ORG
PE
V CC
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
DFN (1)
1
2
3
4
5
6
7
8
TDFN (1)
1
2
3
4
5
6
7
8
SOT-23
5
4
3
1
2
6
Function
Chip Select
Serial Clock
Data In
Data Out
Ground
Organization/93XX86C only
Program Enable/93XX86C only
Power Supply
Note 1:
The exposed pad on the DFN/TDFN package may be connected to Vss or left floating.
3.1
Chip Select (CS)
3.3
Data In (DI)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
Data In (DI) is used to clock in a Start bit, opcode,
address and data, synchronously with the CLK input.
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
3.4
Data Out (DO)
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T CSL ) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (T PD after the
positive edge of CLK).
This pin also provides Ready/ Busy status information
during erase and write cycles. Ready/ Busy status
information is available on the DO pin if CS is brought
3.2
Serial Clock (CLK)
high after being low for minimum Chip Select low time
(T CSL ), and an erase or write operation has been
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
initiated.
The Status signal is not available on DO if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T CKH ) and
clock low time (T CKL ). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
Note:
3.5
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/ Busy status from DO.
Organization (ORG)
detected (DI = 0 ), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don't care” inputs waiting for a new Start
condition to be detected.
? 2003-2012 Microchip Technology Inc.
When the ORG pin is connected to V CC or logic high,
the (x16) memory organization is selected. When the
ORG pin is tied to V SS or logic low, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX86A devices are always (x8) organization and
93XX86B devices are always (x16) organization.
DS21797L-page 11
相关PDF资料
93LC46A-I/PG IC EEPROM 1KBIT 2MHZ 8DIP
93LC56AX/SN IC EEPROM 2KBIT 3MHZ 8SOIC
93LC66BXT/SN IC EEPROM 4KBIT 2MHZ 8SOIC
93LC66XT/SN IC EEPROM 4KBIT 2MHZ 8SOIC
93LC86/P IC EEPROM 16KBIT 3MHZ 8DIP
94104-044LF 94104-044LF PCB MJ LOW PROFILE
94152-088LF CONN MOD JACK 8-8 VERT PCB SHLD
9436-7600 CONN SOCKET 36POS CLOSED END
相关代理商/技术参数
93C86C-I/PG 功能描述:电可擦除可编程只读存储器 1024x16-2048x8 Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93C86C-I/S15K 功能描述:电可擦除可编程只读存储器 16K, 1024 X 16 OR 2048 X 8 SERIAL EE DIE in WAFFLE PK IND RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93C86C-I/SN 功能描述:电可擦除可编程只读存储器 1024x16-2048x8 5.0V IND TEMP, SOIC8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93C86C-I/SNG 功能描述:电可擦除可编程只读存储器 1024x16-2048x8 Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93C86C-I/ST 功能描述:电可擦除可编程只读存储器 1024x16-2048x8 5.0V IND TMP, TSSOP8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93C86C-I/STG 功能描述:电可擦除可编程只读存储器 1024x16-2048x8 Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93C86C-I/W15K 功能描述:电可擦除可编程只读存储器 16K, 1024 X 16 OR 2048 X 8 SERIAL EE WAFER,IND RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93C86C-I/WF15K 功能描述:电可擦除可编程只读存储器 16K, 1024 X 16 OR 2048 X 8 SERIAL EE WAFER ON FR,IND RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8